`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 		PI3
// Engineer: 		Matthias Niethammer
// 
// Create Date:    17:31:33 10/15/2010 
// Design Name: 
// Module Name:    reg_counter_down
// Project Name: 
// Target Devices: 
// Tool versions:	ISE 11.1
// Description: 	register based downwards counter with variable width and overflow flag 
//
// Dependencies: 	none
//
// Revision: 
// Revision 0.03 - copied from upwards counter and switched counting direction
// 					 start value added
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module reg_counter_down #( parameter N = 10, UNDER = 0, START = 0 )
(
    input clk,
    input enable,
    input reset,
    output [N-1:0] out,
	 output underflow
    );


reg [N-1:0] temp = START;
reg under;
assign out[N-1:0] = temp[N-1:0];
assign underflow = under;

always@( posedge clk , posedge reset)
begin

		if( reset )
		begin
			temp <= 0;
			under <= 0;
		end
		else if ( enable)
		begin
			temp <= temp - 1;
			if( temp == UNDER )
				under <= 1;
			else
				under <= 0;
		end
end
			

endmodule
